Roles

Floating-point design lead for the native K7, architect and technical manager for floating-point instructions development on the K5. Participated in IP development for signal processing efforts. Played roles as logic designer, circuit designer, tools development, test code generation, and debug on other projects. Mathematician for development of new numerics algorithms and proofs of correctness.

Intellectual Property

These include circuits, logic, and architecture. Was given the AMD "Multiple Patents" award - a thick glass free standing plaque.

Pipeline Predict Proofs

These were formal proofs in lemma form developed along side of development of the 2050 floating point unit pipeline serialization criteria so as to guarantee precise exceptions. After doing these I began writing proofs for my arithmetic algorithms, eventually leading to discussions with Ken Albin, Terry Huett and Dave Read for bringing in a mechanical theorem proving tool into AMD.

A Novel Binary Adder

The insight that lead to the fast adder design, the smallest and fastest in the industry, was that the carry operation is idempotent. To establish that this was indeed the fastest configuration known, I did a thesis at UT Austin, "Binary Adders", that examined all known configurations. That thesis was also the first to present an algorithm, with a C++ implementation, for finding optimum multi-level carry skip adders independent of process.

CS21s Characterization for Synthesis

I designed many circuits at AMD at a time synthesis was just getting started. A critical path timing tool required linear gate models. I took the BSIM device equations for CS21s devices stacked as gates and put in series, then modeled the transfer functions as hyper dimensional surfaces, and found hyper plane fits for those surfaces. It was fascinating to put my device physics course to use, and I came to know Mathematica very well on this project.

Novel Numeric Algorithms and Circuits

For the Am486 and later processors, found a parallel partition for the Binary to BCD problem, which could be run though a pipeline. For the 29050 found a logarithmic barrel shift approach that cut in half the size of the existing circuit that was in use. Designed an SRT divider which simplified the complex quotient prediction logic so much that it double pumped per clock to beat Intel's design, through the patent sharing agreement Intel's apparent copy of the circuit from the patent, was not as successful. Developed the SQRT algorithm for 29050, nothing to write home about. Identified the algorithms to be used on K5 and created the initial implementations. Go to know Hart very well, and came up with many variations on argument reduction and polynomial interpolation.

Floating-point Multiprecision Approach

The architect for the coming K5 did not allow the expansion of the data path for numeric accuracy due to the ramifications throughout the superscalar architecture. Hence I developed a multiprecision method. I initially modified high radix online arithmetic to work with bus-sized digits. As proof of concept I worked with a student at UT on a simple compiler with the objective of seing if the approach would be practical. I broadened the approach to incorporate floating-point digits. I created a library in Mathematica with instructions for this arithmetic, and used it to write and test some of the algorithms would be needed on the K5. I assembled and taksed my K5 floating-point team with writing a Mathematica source to nano-code compiler, writing error analysis programs, doing formal proofs, and furhter developing the source code. The results were superior, with one expert proclaiming it as the most trustworthy numerics available in the industry.